1. Field of the Invention
The present invention relates to a metal-oxidesemiconductor (MOS) field effect transistor structure, formed between field oxide zones of an integrated circuit, with extremely shallow source/drain zones in the silicon substrate and self-aligned source/drain terminals composed of silicide, and a gate electrode which is separated by an insulating layer from the substrate. The gate electrode located between the source/drain zones is provided with a side-wall oxide. The invention further relates to highly-integrated circuits (IC's), containing complementary-metal-oxide-semiconductor (CMOS) transistors, with field oxide zones which separate the active transistor zones, with extremely source/drain zones in the substrate, with selfaligned source/drain terminals composed of silicide, and with gate electrodes located between the source/drain zones of the nchannel and p-channel transistors, so as to be insulated from the substrate, and which are provided with side-wall oxides. The invention further relates to the process for the product of said circuits.
2. Description of the Prior Art
The further miniaturisation of MOS-ICs has resulted in increased problems in respect of parasitic series resistances, drain field strengths (so-called hot carrier effects) and planarisation. Prior to the contact hole etching, the planarisation is particularly restricted due to the number of different contact hole depths which would otherwise occur and due to the limited selectivity of the etching process to the substrate.
For the reduction of the drain field strengths, socalled lightly, doped drain (LDD) techniques are in widespread use, which, however, result in considerable series resistances. Therefore, in order to overcome the problem of the series resistances of the so-called SALICIDE techniques (self-aligned silicide techniques), as described, for example, in a report by C. K. Lau, Y. C. See, D. B. Scott, J. M. Bridges, S. M. Perna and R. D. Davis in the IEDM Technical Digest, 1982, pp. 714-777 and a combination of self-aligned siliciding (deposition of metal onto silicon surfaces) with the lightly-doped-drain technique have been proposed. This technique is known as the so-called SOLID technique (silicide on lightly doped drain) and is disclosed in a report by M. Horiuchi and K. Yamaguchi in the publication "Solid State Electronics", Vol. 28, 1985, pp. 465-472.
The disadvantage of all these techniques is that the previously-produced diffusion zones, which are necessarily shallow because of the short-channel properties, are, in part, consumed as a result of the silicide reaction. As a result there is a high risk of substrate short-circuits, in particular in the case of non-homogeneous reactions.